(1) Field of the Invention
The present invention relates to a process in which Metal Oxide Semiconductor Field Effect Transistors, (MOSFET), devices cart be fabricated using a bilayer structure, a refractory metal silicide on doped polysilicon, for the gate electrode.
(2) Description of Prior Art
Very large scale integration, (VLSI), has helped the semiconductor chip industry increase circuit density while still reducing cost. This has been accomplished in part by advances in lithographic disciplines, reducing image dimension and therefore ultimately reducing chip size and cost. Another factor in the VLSI optimization cycle has been the use of less resistive elements, specifically the use of polycides for gate electrodes. The reduction in resistance for a polycide gate can be as much as 10.times. when compared to polysilicon gate counterparts.
Polycide, which is a bilayer structure comprising a refractory metal silicide on doped polysilicon, can be created by several techniques. A metal, such as titanium, (Ti), or tungstens, (W), can be deposited on a polysilicon film, then annealed at a temperature high enough to form the metal silicide. This process can be performed to a level in which either total consumption of the polysilicon occurs, resulting in a layer of just the metal silicide, or where only partial consumption of the polysilicon occurs resulting a bilayer structure of silicide-polysilicon. The extent of the polysilicon consumption is a function of the time and temperature of the reaction. This process is sometimes referred to as the Self Aligned silicide, or SAlicide method. The self alignment is a result of silicide forming only on regions where the metal interfaces exposed silicon, during some thermal treatment, while remaining unreactive on the insulator surface. A selective wet etch is then used to remove the unreacted metal, while the metal silicide remains intact.
Another technique for obtaining polycides is via deposition of the metal silicide. This is accomplished by sputtering, evaporation or low pressure chemical vapor deposition, (LPCVD), of the metal silicide. This technique is not self aligned, since a blanket deposition is performed. Therefore a patterning process, using reactive ion etching, (RIE), is used to obtain the desired shapes of the metal silicide on polysilicon. This method of forming polycides has been shown by C. Yoo et al in U.S. Pat. No. 5,089,432, and by Watanabe et al in an article entitled "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMS", in "Symposium on VLSI Technology", 1993, pp 17-18.
A major problem with polycide technology has been the lack of adhesion, or subsequent peeling of the refractory metal silicide from the the underlying doped polysilicon surface. The peeling occurs as a result of the relaxation of thermal stress between the metal silicide and the polysilicon layers. Factors enhancing the adhesion loss are the high level of dopant at the polysilicon surface and the native oxide at the polysilicon surface.
It is therefore an object of this invention to provide a method for fabricating devices with polycides that overcome this peeling or adhesion loss phenomena.